1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a high speed programmable Read Only Memory (ROM) system.
2. Description of the Related Art
Mask ROM is a semiconductor memory device in which a user codes needed data in advance on the memory device in a manufacturing process so that the coded data can be repeatedly read later. Mask ROMs include an embedded diffusion-programmable ROM and an embedded metal-programmable ROM. For the embedded diffusion-programmable ROM, a ROM data code is determined in a diffusion process in the manufacturing processes, while for the embedded metal-programmable ROM, a ROM data code is determined in a metal processing process in the manufacturing processes.
Meanwhile, there is an embedded contact programmable ROM or an embedded via programmable ROM which is almost the same as the embedded metal-programmable ROM. For the embedded contact programmable ROM, a ROM data code is determined in a contact processing process in the manufacturing processes, while for the embedded via programmable ROM, a ROM data code is determined in a via processing process in the manufacturing processes.
Generally, the embedded diffusion-programmable ROM has been preferred over the embedded metal-programmable ROM, mainly because the former can achieve an integration about 25% higher than that of the latter.
However, the embedded diffusion-programmable ROM has a longer time interval from when data from a user is received to when a completed product is manufactured, that is, the turn-around time of the embedded diffusion-programmable ROM is longer than that of the embedded metal-programmable ROM. Recently, thanks to technology development in semiconductor manufacturing processes, integration of the embedded metal (or via)-programmable ROM has greatly increased, and the importance of the embedded metal (or via)-programmable ROM which is advantageous in Time-to-Market has increased.
FIG. 1 is a diagram showing the cell array structure in a prior art metal programmable ROM. For convenience of explanation, FIG. 1 shows a 4×4 bit cell array structure formed with 2 bit lines BL0 and BL1, 3 virtual ground lines VG0˜VG2, 4 word lines WL0˜WO3, and 16 cell transistors M1˜M16. Here, a virtual ground line is a line which is selectively connected to ground by a switch (not shown). Also, capacitors C1˜C4 of FIG. 1 show not actual circuit elements but coupling capacitance between lines. C5 is a total capacitance of bit line BL0, and C6 is a total capacitance of bit line BL1.
Referring to FIG. 1, the gate of each of 16 cell transistors M1˜M16 is connected to a word line, and the source of each transistor M1˜M16 is connected to a virtual ground line. The drain of each transistor M1˜M16 can be electrically connected to a bit line selectively to program the cell transistor. That is, by electrically connecting the drain of a cell transistor M1˜M16 to a bit line, the cell transistor is programmed to have “0”, and by floating the drain, the transistor is programmed to have “1”. Meanwhile, the speed of the programmable ROM depends on a total capacitance loaded on a bit line. The total capacitance loaded on a bit line determines a time interval from when a bit line is precharged to when the bit line is discharged. Accordingly, if the total capacitance is big, the overall operation speed of the ROM is lowered.
Also, a ratio of a coupling capacitance between a bit line and a neighboring line to the total capacitance of the bit line is an important factor in evaluating a programmable ROM. If this ratio is big, the transition in the neighboring line interferes the bit line, and the bit line which is precharged may not be able to maintain the precharged state and therefore may cause to misread ROM data. To prevent this error, the ratio of a coupling capacitance between the bit line and a neighboring line to the total capacitance of the bit line is made to be small. For this, the total capacitance loaded on a bit line should be increased, but this causes a decrease in speed.
In the programmable ROM of FIG. 1, cells connected to bit line BL0 are programmed to have “0”, and cells connected to bit line BL1 are programmed to have “1”. At this time, total capacitance C5 loaded to bit line BL0 becomes the maximum, total capacitance C6 loaded to bit line BL1 becomes the minimum, and the operation speed of the programmable ROM is determined by bit line BL0.
Here, factors affecting the capacitance of bit line BL0 are capacitance by the bit line length, capacitance by the programming metal line 28, capacitance by a contact CNT1 connected to the bit line, and capacitance by transistors M1˜M8 connected to the bit line. The total capacitance C5 of bit line BL0 has a very big value due to the influence of these capacitances, and accordingly the speed of the programmable ROM is lowered. However, as the ratio of the coupling capacitance between the bit line BL0 and the neighboring line VG0 or VG1 to the total capacitance of the bit line BL0 (=C1/C5, or C2/C5) becomes smaller, misreading ROM data due to a coupling capacitance with a neighboring line can be prevented.
Meanwhile, since an only factor affecting the capacitance of bit line BL1 is capacitance by the bit line length, the total capacitance C6 of bit line BL1 has a very smaller value than C5. Therefore, as the ratio of the coupling capacitance between the bit line BL1 and the neighboring line VG1 or VG2 to the total capacitance of the bit line BL1 (=C3/C6, or C4/C6) becomes bigger, misreading ROM data of cells connected to the bit line BL1 due to a coupling capacitance may occur. Thus, in order to prevent misreading ROM data due to a coupling capacitance, when ROM data is read, the operation speed of a sense amplifier should be decreased, or precharge and discharge time should be appropriately adjusted to avoid interference, but both cause decrease in the speed of the ROM.